View ISL6752AAZA_3453226.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? fn9181.3 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005, 2006, 2008. all rights reserved all other trademarks mentioned are the property of their respective owners. isl6752 zvs full-bridge current-mode pwm with adjustable synchronous rectifier control the isl6752 is a high-performanc e, low-pin-count alternative zero-voltage switching (zvs) full-bridge pwm controller. like intersil?s isl6551, it achieves zvs operation by driving the upper bridge fets at a fixed 50% duty cycle while the lower bridge fets are trailing-edge modulated with adjustable resonant switching delays. compared to the more familiar phase-shifted control method, this algorithm offers equivalent efficiency and improved overcurr ent and light-load performance with less complexity in a lower pin count package. the isl6752 features comp lemented pwm outputs for synchronous rectifier (sr) control. the complemented outputs may be dynamically advanced or delayed relative to the pwm outputs using an external control voltage. this advanced bicmos design features precision deadtime and resonant delay control, and an oscillator adjustable to 2mhz operating frequency. additionally, multi-pulse suppression ensures alternatin g output pulses at low duty cycles where pulse skipping may occur. features ? adjustable resonant delay for zvs operation ? synchronous rectifier control outputs with adjustable delay/advance ? current-mode control ? 3% current limit threshold ? adjustable deadtime control ? 175a start-up current ? supply uvlo ? adjustable oscillator frequency up to 2mhz ? internal over-tem perature protection ? buffered oscillator sawtooth output ? fast current sense to output delay ? adjustable cycle-by-cycle peak current limit ? 70ns leading edge blanking ? multi-pulse suppression ? pb-free (rohs compliant) applications ? zvs full-bridge converters ? telecom and datacom power ? wireless base station power ? file server power ? industrial power systems pinout isl6752 (16 ld qsop) top view ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL6752AAZA* isl 6752aaz -40 to +105 16 ld qsop m16.15a *add ?-t? suffix for tape and reel. please refer to tb347 for details on reel specifications. note: these intersil pb-free pl astic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 vadj vref verr ctbuf rtd resdel cs ct vdd outlr outul outur outlln outlrn gnd outll data sheet october 31, 2008
2 fn9181.3 october 31, 2008 isl6752 functional block diagram outll outlr outul outur vdd pwm steering logic resdel uvlo over- temperature protection vref oscillator ct rtd vdd gnd vref + - 0.33 80mv vref 50% pwm verr 1ma ctbuf cs pwm comparator + - 1.00v overcurrent comparator 70ns leading edge blanking outlln outlrn delay/ advance timing control vadj
3 fn9181.3 october 31, 2008 isl6752 typical application - high voltage input prim ary side control zvs full-bridge converter vin+ vin- return t2 r7 c15 c2 r1 r3 r2 q11 400 vdc u1 l1 t1 r5 vr1 r8 + v out c7 c1 q2 q3 r11 r10 r12 r13 c6 c3 c10 c9 c8 c12 c13 t3 q5a q5b q8a q8b cr3 cr2 + + q6a q6b q7a q7b vdd r14 r15 c11 c14 u3 r16 r17 r18 q9a q9b q10a q10b u2 cr1 q1 q4 r4 r6 c4 verr outll rtd outlrn outlln vref outur ctbuf ct outul resdel outlr vadj vdd cs gnd isl6752 u5 u4 t4 c5 r19 r20 r21 r22 r23 r24 cr4 q12 q13 r23 c16 q14 r24 el7212 el7212 c17
4 fn9181.3 october 31, 2008 isl6752 typical application - high volt age input secondary side cont rol zvs full-bridge converter vin+ vin- return t2 r6 c13 c2 400 vdc u1 l1 t1 np:ns:ns = 9:2:2 r2 r8 + v out c14 c1 q2 q3 r12 r13 r15 r14 c5 c3 c10 c12 c11 t3 1:1:1 q5 cr3 cr2 + + secondary bias supply r19 r18 c15 c16 u3 r17 q9a q9b q10a q10b cr1 q1 q4 r1 r3 c4 verr outll rtd outlrn outlln vref outur ctbuf ct outul resdel outlr vadj vdd cs gnd isl6752 r7 r9 r4 r5 q16 q15 c7 q12a q12b q11a q11b r11 cr5 r10 cr4 q13a q13b q14a q14b q7a q7b c8 q8a q8b q6 t4 1:1:1 c9 c17 r20 r16 q17 np ns ns c6 + - vref r22 r21 c18 vref
5 fn9181.3 october 31, 2008 absolute maxi mum ratings (note 2) thermal information supply voltage, vdd . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +20.0v outxxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to vdd signal pins . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to v ref + 0.3v vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 6.0v peak gate current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1a operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +105c supply voltage range (typical). . . . . . . . . . . . . . . . 9vdc to 16vdc thermal resistance junction to ambient (typical) ja (c/w) 16 ld qsop (note 1). . . . . . . . . . . . . . . . . . . . . . . . 100 maximum junction temperature . . . . . . . . . . . . . . .-55c to +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 2. all voltages are with respect to gnd. electrical specifications recommended operating conditions unles s otherwise noted. refer to ?func tional block diagram? on page 2 and ?typical application - high volt age input primary side control zvs full-bridge converter? on page 3 and ?typical application - high voltage input secondary side control zvs full-bridge converter? on page 4. 9v < vdd < 20v, rtd = 10.0k , ct = 470pf, t a = -40c to +105c, typical values are at t a =+25c; parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characteri zation and are not production tested. parameter test conditions min typ max units supply voltage supply voltage --20v start-up current, i dd v dd = 5.0v - 175 400 a operating current, i dd r load , c out = 0 - 11.0 15.5 ma uvlo start threshold 8.00 8.75 9.00 v uvlo stop threshold 6.50 7.00 7.50 v hysteresis -1.75-v reference voltage overall accuracy i vref = 0ma to 10ma 4.850 5.000 5.150 v long term stability t a = +125c, 1000 hours (note 3) - 3 - mv operational current (source) -10 - - ma operational current (sink) 5- -ma current limit vref = 4.85v -15 - -100 ma current sense current limit threshold verr = vref 0.97 1.00 1.03 v cs to out delay excl. leb (note 3) - 35 50 ns leading edge blanking (leb) duration (note 3) 50 70 100 ns cs to out delay + leb t a = +25c - - 130 ns cs sink current device impedance v cs = 1.1v - - 20 input bias current v cs = 0.3v -6.00 - -2.00 a cs to pwm comparator input offset t a = +25c 65 80 95 mv pulse width modulator verr pull-up current source verr = 2.50v 0.80 1.00 1.30 ma verr voh i load = 0ma 4.20 - - v minimum duty cycle verr < 0.6v - - 0 % isl6752
6 fn9181.3 october 31, 2008 maximum duty cycle (per half-cycle) verr = 4.20v, v cs = 0v (note 4) - 94 - % rtd = 2.00k , ct = 220pf - 97 - % rtd = 2.00k , ct = 470pf - 99 - % zero duty cycle verr voltage 0.85 - 1.20 v verr to pwm comparator input offset t a = +25c 0.7 0.8 0.9 v verr to pwm comparator input gain 0.31 0.33 0.35 v/v common mode (cm) input range (note 3) 0 - 4.45 v oscillator frequency accuracy, overall (note 3) 165 183 201 khz -10 - 10 % frequency variation with vdd t a = +25c, (f 20v - - f 10v )/f 10v -0.31.7% temperature stability vdd = 10v, |f -40c - f 0c |/f 0c -4.5-% |f 0c - f 105c |/f 25c (note 3) - 1.5 - % charge current t a = +25c -193 -200 -207 a discharge current gain 19 20 23 a/a ct valley voltage static threshold 0.75 0.80 0.88 v ct peak voltage static threshold 2.75 2.80 2.88 v ct pk-pk voltage static value 1.92 2.00 2.05 v rtd voltage 1.97 2.00 2.03 v resdel voltage range 0 - 2.00 v ctbuf gain (v ctbufp-p /v ctp-p )v ct = 0.8v, 2.6v 1.95 2.0 2.05 v/v ctbuf offset from gnd v ct = 0.8v 0.34 0.40 0.44 v ctbuf voh v(i load = 0ma, i load = -2ma), v ct = 2.6v - - 0.10 v ctbuf vol v(i load = 2ma, i load = 0ma), v ct = 0.8v - - 0.10 v output high level output voltage (voh) i out = -10ma, vdd - voh - 0.5 1.0 v low level output voltage (vol) i out = 10ma, vol - gnd - 0.5 1.0 v rise time c out = 220pf, vdd = 15v (note 3) - 110 200 ns fall time c out = 220pf, vdd = 15v (note 3) - 90 150 ns uvlo output voltage clamp vdd = 7v, i load = 1ma (note 5) - - 1.25 v output delay/advance range outlln/outlrn relative to outll/outlr v adj = 2.50v (note 3) - - 3 ns v adj < 2.425v -40 - -300 ns v adj > 2.575v 40 - 300 ns delay/advance control voltage range outlln/outlrn relative to outll/outlr outlxn delayed 2.575 - 5.000 v outlxn advanced 0 - 2.425 v electrical specifications recommended operating conditions unles s otherwise noted. refer to ?func tional block diagram? on page 2 and ?typical application - high volt age input primary side control zvs full-bridge converter? on page 3 and ?typical application - high voltage input secondary side control zvs full-bridge converter? on page 4. 9v < vdd < 20v, rtd = 10.0k , ct = 470pf, t a = -40c to +105c, typical values are at t a =+25c; parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characteri zation and are not production tested. (continued) parameter test conditions min typ max units isl6752
7 fn9181.3 october 31, 2008 vadj delay time t a = +25c (outlx delayed) (note 6) vadj = 0 280 300 320 ns vadj = 0.5v 92 105 118 ns vadj = 1.0v 61 70 80 ns vadj = 1.5v 48 55 65 ns vadj = 2.0v 41 50 58 ns t a = +25c (outlxn delayed) vadj = vref 280 300 320 ns vadj = vref - 0.5v 86 100 114 ns vadj = vref - 1.0v 59 68 77 ns vadj = vref - 1.5v 47 55 62 ns vadj = vref - 2.0v 41 48 55 ns thermal protection thermal shutdown (note 3) 130 140 150 c thermal shutdown clear (note 3) 115 125 135 c hysteresis, internal protection (note 3) - 15 - c notes: 3. limits established by characteri zation and are not production tested.. 4. this is the maximum duty cy cle achievable using the specified values of rt d and ct. larger or smaller maximum duty cycles may be obtained using other values for these components. see equations 1 through 3. 5. adjust vdd below the uvlo stop threshold prior to setting at 7v. 6. when outx is delayed relative to outlxn (vadj < 2.425v), the delay duration as set by vadj s hould not exceed 90% of the ct di scharge time (deadtime) as determined by ct and rtd. electrical specifications recommended operating conditions unles s otherwise noted. refer to ?func tional block diagram? on page 2 and ?typical application - high volt age input primary side control zvs full-bridge converter? on page 3 and ?typical application - high voltage input secondary side control zvs full-bridge converter? on page 4. 9v < vdd < 20v, rtd = 10.0k , ct = 470pf, t a = -40c to +105c, typical values are at t a =+25c; parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characteri zation and are not production tested. (continued) parameter test conditions min typ max units typical performance curves figure 1. reference voltage vs temperature figu re 2. ct discharge current gain vs rtd current -40 -25 -10 5 20 35 50 65 80 95 110 0.98 0.99 1.00 1.01 1.02 temperature (c) normalized vref 0 200 400 600 800 1000 18 19 20 21 22 23 24 25 rtd current (a) ct discharge current gain isl6752
8 fn9181.3 october 31, 2008 pin descriptions vdd - vdd is the power connection for the ic. to optimize noise immunity, bypass vdd to gnd with a ceramic capacitor as close to the vdd and gnd pins as possible. vdd is monitored for supply voltage undervoltage lock-out (uvlo). the start and stop thresholds track each other resulting in relatively constant hysteresis. gnd - signal and power ground connections for this device. due to high peak currents and high frequency operation, a low impedance layout is necessary. ground planes and short traces are highly recommended. vref - the 5.00v reference voltage output having 3% tolerance over line, load and operating temperature. bypass to gnd with a 0.1f to 2.2f low esr capacitor. ct - the oscillator timing capacitor is connected between this pin and gnd. it is charged through an internal 200a current source and discharged with a user adjustable current source controlled by rtd. rtd - this is the oscillator timing capacitor discharge current control pin. the current flowing in a resistor connected between this pi n and gnd determines the magnitude of the current that discharges ct. the ct discharge current is nominally 20x the resistor current. the pwm deadtime is determined by the timing capacitor discharge duration. the voltage at rtd is nominally 2v. cs - this is the input to the overcurrent comparator. the overcurrent comparator threshold is set at 1v nominal. the cs pin is shorted to gnd at the termination of either pwm output. depending on the current sens ing source impedance, a series input resistor may be required due to the delay between the internal clock and the external power switch. this delay may result in cs being discharged prior to the power switching device being turned off. outul and outur - these outputs control the upper bridge fets and operate at a fixed 50% duty cycle in alternate sequence. outul controls the upper left fet and outur controls the upper right fet. the left and right designation may be switched as long as they are switched in conjunction with the lower fet outputs, outll and outlr. resdel - sets the resonant delay period between the toggle of the upper fets and t he turn on of either of the lower fets. the voltage applied to resdel determines when the upper fets switch relative to a lower fet turning on. varying the control voltage from 0v to 2v increases the resonant delay duration from 0 to 100% of the deadtime. the control voltage divided by 2 represents the percent of the deadtime equal to the resonant delay. in practice the maximum resonant delay must be set lower than 2v to ensure that the lower fets, at maximum duty cycle, are off prior to the switching of the upper fets. outll and outlr - these outputs control the lower bridge fets, are pulse width modulated, and operate in alternate sequence. outll controls the lower left fet and outlr controls the lower right fet. the left and right designation may be switched as long as they are switched in conjunction with the upper fet outputs, outul and outur. outlln and outlrn - these outputs are the complements of the pwm (lower) bridge fets. outlln is the complement of outll and outlrn is the complement of outlr. these outputs are suitable for control of synchronous rectifiers. the phase relationship between each output and its complement is controlled by the voltage applied to vadj. vadj - a 0v to 5v control voltage applied to this input sets the relative delay or advance between outll/outlr and outlln/outlrn. the phase relationship between outul/outur and outll/outlr is maintained regardless of the phase adju stment between outll/outlr and outlln/outlrn. figure 3. deadtime (dt) vs capacita nce figure 4. capacitance vs frequency typical performance curves (continued) 0 102030405060708090100 10 100 rtd (k ) deadtime td (ns) 1-10 4 1-10 3 ct = 1000pf ct = 680pf ct = 470pf ct = 330pf ct = 220pf ct = 100pf 0.1 1 10 10 100 ct (nf) frequency (khz) 1-10 3 rtd = 10k rtd = 50k rtd = 100k isl6752
9 fn9181.3 october 31, 2008 voltages below 2.425v result in outlln/outlrn being advanced relative to outll/outlr. voltages above 2.575v result in outlln/outlrn being delayed relative to outll/outlr. a voltage of 2. 50v 75mv results in zero phase difference. a weak internal 50% divider from vref results in no phase delay if this input is left floating. the range of phase delay/advance is either zero or 40ns to 300ns with the phase differential increasing as the voltage deviation from 2.5v increases. the relationship between the control voltage and phase differential is non-linear. the gain ( t/ v) is low for control voltages near 2.5v and rapidly increases as the voltage approa ches the extremes of the control range. this behavior provides the user increased accuracy when selecting a shorter delay/advance duration. when the pwm outputs are delayed relative to the sr outputs (vadj < 2.425v), the delay time should not exceed 90% of the deadtime as determined by rtd and ct. verr - the control voltage input to the inverting input of the pwm comparator. the output of an external error amplifier (ea) is applied to this input, either directly or through an opto-coupler, for closed loop regulation. verr has a nominal 1ma pull-up current source. ctbuf - ctbuf is the buffered output of the sawtooth oscillator waveform present on ct and is capable of sourcing 2ma. it is offset from ground by 0.40v and has a nominal valley-to-peak gain of 2. it may be used for slope compensation. functional description features the isl6752 pwm is an excellent choice for low cost zvs full-bridge applications requiring adjustable synchronous rectifier drive. with its many protection and c ontrol features, a highly flexible design with minimal external components is possible. among its many feat ures are a very accurate overcurrent limit threshold, thermal protection, a buffered sawtooth oscillator output suit able for slope compensation, synchronous rectifier outputs with variable delay/advance timing, and adjustable frequency. if synchronous rectification is not required, please consider the isl6753 controller. oscillator the isl6752 has an oscillator with a programmable frequency range to 2mhz, which can be programmed with a resistor and capacitor. the switching period is the sum of the timing capacitor charge and discharge durations. the charge duration is determined by ct and a fixed 200a internal current source. the discharge duration is determined by rtd and ct. where t c and t d are the charge and discharge times, respectively, ct is the timing capacitor in farads, rtd is the discharge programming resistance in ohms, t sw is the oscillator period, and f sw is the oscillator frequency. one output switching cycle requires two oscillator cycles. the actual times will be slightly longer than calculated due to internal propagation delays of approximately 10ns/transition. this delay adds directly to t he switching duration, but also causes overshoot of the timing capacitor peak and valley voltage thresholds, effectively increasing the peak-to-peak voltage on the timing capacitor. additionally, if very small discharge currents are used, there will be increased error due to the input impedance at the ct pin. the maximum recommended current through rtd is 1ma, which produces a ct discharge current of 20ma. the maximum duty cycle, d, and percent deadtime, dt, can be calculated from equations 4 and 5: implementing soft-start the isl6752 does not have a soft -start feature. soft-start can be implemented externally using the components shown in the following. the rc network governs the rate of rise of the transistor?s base, which clamps the voltage at verr. t c 11.5 10 ? 3 ct ? s (eq. 1) t d 0.06 rtd ct ?? () 50 10 9 ? ? + s (eq. 2) t sw t c t d + 1 f sw ------------ == s (eq. 3) d t c t sw ---------- = (eq. 4) dt 1 d ? = (eq. 5) figure 5. implementing soft-start vref 1 2 4 3 5 6 7 89 1 0 1 1 1 2 1 3 1 4 1 5 1 6 isl6752 verr r c isl6752
10 fn9181.3 october 31, 2008 the values of r and c should be selected to control the rate of rise of verr to the desired soft-start duration. the soft-start duration may be calculated from equation 6. where v ss is the soft-start clamp voltage, v be is the base emitter voltage drop of the transistor, and is the dc gain of the transistor. if is sufficiently large, that term may be ignored. the schottky diode discharges the soft-start capacitor so that the ci rcuit may be reset quickly. gate drive the isl6752 outputs are capable of sourcing and sinking 10ma (at rated voh, vol) and are intended to be used in conjunction with integrated fet drivers or discrete bipolar totem pole drivers. the typical on-resistance of the outputs is 50 . overcurrent operation the cycle-by-cycle peak current control results in pulse-by-pulse duty cycle r eduction when the current feedback signal exceeds 1.0v. when the peak current exceeds the threshold, the active output pulse is immediately terminated. this results in a well controlled decrease in output voltage as the load current increases beyond the current limit threshold. the isl6752 will operate continuously in an overcurrent condition. the propagation delay from cs exceeding the current limit threshold to the termination of the output pulse is increased by the leading edge blanking (leb) interval. the effective delay is the sum of the two delays and is nominally 105ns. slope compensation peak current-mode control requires slope compensation to improve noise immunity, particular ly at lighter loads, and to prevent current loop instability, particularly for duty cycles greater than 50%. slope compensation may be accomplished by summing an external ramp with the current feedback signal or by subtracting the external ramp from the voltage feedback error signal. adding the external ramp to the current feedback signal is the more popular method. from the small signal curr ent-mode model [1] it can be shown that the naturally-sampled modulator gain, fm, without slope compensation, is expressed in equation 7: where s n is the slope of the sawtooth signal and t sw is the duration of the half-cycle. when an external ramp is added, the modulator gain becomes equation 8: where s e is slope of the external ramp and: the criteria for determining the correct amount of external ramp can be determined by appropriately setting the damping factor of the double- pole located at half the oscillator frequency. the d ouble-pole will be critically damped if the q-factor is set to 1, and over-damped for q > 1, and under-damped for q < 1. an under-damped condition can result in current loop instability. where d is the percent of on-ti me during a half cycle. setting q = 1 and solving for s e yields equation 11: since s n and s e are the on-time slopes of the current ramp and the external ramp, respecti vely, they can be multiplied by t on to obtain the voltage change that occurs during t on . where v n is the change in the current feedback signal during the on-time and v e is the voltage that must be added by the external ramp. v n can be solved for in terms of input voltage, current transducer components, and output inductance yielding equation 13: where r cs is the current sense burden resistor, n ct is the current transformer turns ratio, l o is the output inductance, v o is the output voltage, and n s and n p are the secondary and primary turns, respectively. the inductor current, when reflected through the isolation transformer and the current sense transformer to obtain the current feedback signal at the sense resistor yields equation 14: where v cs is the voltage across the current sense resistor and i o is the output current at current limit. trc ? 1 v ss v be ? vref 0.001r ------------------- + ------------------------------------------- ? ?? ?? ?? ?? ln ? = s (eq. 6) fm 1 s n t sw ----------------- - = (eq. 7) fm 1 s n s e + () t sw ------------------------------------ 1 m c s n t sw -------------------------- == (eq. 8) m c 1 s e s n ------ - + = (eq. 9) q 1 m c 1d ? () 0.5 ? () ------------------------------------------------- = (eq. 10) s e s n 1 -- - 0.5 + ?? ?? 1 1d ? ------------- 1 ? ?? ?? = (eq. 11) v e v n 1 -- - 0.5 + ?? ?? 1 1d ? ------------- 1 ? ?? ?? = (eq. 12) v e t sw v ? o r cs ? n ct l o ? --------------------------------------- - n s n p ------- - ? 1 -- - d0.5 ? + ?? ?? = v (eq. 13) v cs n s r cs ? n p n ct ? ------------------------ i o dt ? sw 2l o ------------------- v in n s n p ------- - ? v o ? ?? ?? ?? + ?? ?? ?? = v (eq. 14) isl6752
11 fn9181.3 october 31, 2008 since the peak current limit threshold is 1.00v, the total current feedback signal plus the external ramp voltage must sum to this value. substituting equations 13 and 14 into equation 15 and solving for r cs yields equation 16: for simplicity, idealized components have been used for this discussion, but the effect of magnetizing inductance must be considered when determining the amount of external ramp to add. magnetizing inductance provides a degree of slope compensation to the current feedback signal and reduces the amount of external ramp required. the magnetizing inductance adds primary curre nt in excess of what is reflected from the inductor current in the secondary. where v in is the input voltage that corresponds to the duty cycle d and l m is the primary magne tizing inductance. the effect of the magnetizing cu rrent at the current sense resistor, r cs , is expressed in equation 18: if v cs is greater than or equal to v e , then no additional slope compensation is needed and r cs becomes equation 19: if v cs is less than v e , then equation 16 is still valid for the value of r cs , but the amount of slope compensation added by the external ramp must be reduced by v cs . adding slope compensation may be accomplished in the isl6752 using the ctbuf signal. ctbuf is an amplified representation of the sawtooth signal that appears on the ct pin. it is offset from ground by 0.4v and is 2x the peak-to-peak amplitude of ct (0.4v to 4.4v). a typical application sums this signal with the current sense feedback and applies the result to the cs pin, as shown in figure 6. assuming the designer has selected values for the rc filter placed on the cs pin, the value of r9 required to add the appropriate external ramp can be found by superposition. rearranging to solve for r9 yields equation 21: the value of r cs determined in equation 16 must be rescaled so that the current s ense signal presented at the cs pin is that predicted by equation 14. the divider created by r6 and r9 makes this necessary. example: v in = 280v v o = 12v l o = 2.0h np/ns = 20 lm = 2mh i o = 55a oscillator frequency, f sw = 400khz duty cycle, d = 85.7% n ct = 50 r6 = 499 solve for the current sense resistor, r cs , using equation 16. r cs = 15.1 . v e v cs + 1 = (eq. 15) r cs n p n ct ? n s ------------------------ 1 i o v o l o ------- - t sw 1 -- - d 2 --- - + ?? ?? + ---------------------------------------------------- ? = (eq. 16) i p v in dt sw ? l m ----------------------------- = a (eq. 17) v cs i p r cs ? n ct ------------------------- - = v (eq. 18) r cs n ct n s n p ------- - i o dt sw 2l o --------------- v in n s n p ------- - ? v o ? ?? ?? ?? ? + ?? ?? ?? ? v in dt sw ? l m ----------------------------- + ------------------------------------------------------------------------------------------------------------------------------- -- - = (eq. 19) figure 6. adding slope compensation r6 c4 r9 ctbuf cs 1 2 4 3 5 6 7 89 10 11 12 13 14 15 16 r cs isl6752 v e v cs ? dv ctbuf 0.4 ? () 0.4 + () r6 ? r6 r9 + ------------------------------------------------------------------------------- = v (eq. 20) r9 dv ctbuf 0.4 ? () v e v cs 0.4 ++ ? () r6 ? v e v cs ? ------------------------------------------------------------------------------------------------------------------ - = (eq. 21) r cs r6 r9 + r9 ---------------------- r cs ? = (eq. 22) isl6752
12 fn9181.3 october 31, 2008 determine the amount of voltage, v e , that must be added to the current feedback signal using equation 13. v e = 153mv next, determine the effect of the magnetizing current from equation 18. v cs = 91mv using equation 21, solve for the summing resistor, r9, from ctbuf to cs. r9 = 30.1k determine the new value of r cs , r? cs , using equation 22. r? cs = 15.4 this discussion determines the minimum external ramp that is required. additional slope compensation may be considered for design margin. if the application requires de adtime of less than about 500ns, the ctbuf signal may not perform adequately for slope compensation. ctbuf lags the ct sawtooth waveform by 300ns to 400ns. this behavior results in a non-zero value of ctbuf when the next half-cycle begins when the deadtime is short. under these situations, slope compensation may be added by externally buffering the ct signal as shown in figure 7. using ct to provide slope compensation instead of ctbuf requires the same calculations , except that equations 20 and 21 require modification. equation 20 becomes: and equation 21 becomes: the buffer transistor used to create the external ramp from ct should have a sufficiently high gain (>200) so as to minimize the required base current. whatever base current is required reduces the charging current into ct and will reduce the oscillator frequency. zvs full-bridge operation the isl6752 is a full-bridge zero-voltage switching (zvs) pwm controller that behaves much like a traditional hard switched topology controller. rather than drive the diagonal bridge switches simultaneously, the upper switches (outul, outur) are driven at a fixe d 50% duty cycle and the lower switches (outll, outlr) are pulse width modulated on the trailing edge. to understand how the zvs method operates, one must include the parasitic elements of the circuit and examine a full switching cycle. in figure 9, the power semiconductor switches have been replaced by ideal switch elements with parallel diodes and capacitance, the output re ctifiers are ideal, and the transformer leakage inductance has been included as a discrete element. the parasitic capacitance has been lumped together as switch capacitance, but represents all parasitic capacitance in the circuit including winding r6 c4 r9 r cs ct ct cs 1 2 4 3 5 6 7 8 isl6752 vref figure 7. adding slope compensation using ct v e v cs ? 2d r6 ? r6 r9 + ---------------------- = v (eq. 23) r9 2d v e v cs + ? () r6 ? v e v cs ? ------------------------------------------------------------ - = (eq. 24) figure 8. bridge drive signal timing ct deadtime outll outlr outur outul resdel window resonant delay pwm pwm pwm pwm figure 9. idealized full-bridge vin+ vin- ul ll ur lr vout+ rtn l l d2 d1 isl6752
13 fn9181.3 october 31, 2008 capacitance. each switch is designated by its position; upper left (ul), upper right (ur), lower left (ll), and lower right (lr). the beginning of the cycle, shown in figure 10, is arbitrarily set as having switches ul and lr on and ur and ll off. the direction of the primary and secondary currents are indicated by i p and i s , respectively. the ul - lr power transfer period terminates when switch lr turns off as determined by the pwm. the current flowing in the primary cannot be inte rrupted instantaneously, so it must find an alternate path. the current flows into the parasitic switch capacitance of lr and ur, which charges the node to vin and then forward biases the body diode of upper switch ur. the primary leakage inductance, l l , maintains the current, which now circulates around t he path of switch ul, the transformer primary, and switch ur. when switch lr opens, the output inductor current fr ee-wheels through both output diodes, d1 and d2. during the switch transition, the output inductor current assists the leakage inductance in charging the upper and lower bridge fet capacitance. the current flow from the pr evious power transfer cycle tends to be maintained during the free-wheeling period because the transformer primary winding is essentially shorted. diode d1 may conduct very little or none of the free-wheeling current, depending on circuit parasitics. this behavior is quite different than occurs in a conventional hard-switched full-bridge topology where the free-wheeling current splits nearly evenly between the output diodes, and flows not at all in the primary. this condition persists through the remainder of the half cycle. during the period when ct discharges (also referred to as the deadtime), the upper switches toggle. switch ul turns off and switch ur turns on. the actual timing of the upper switch toggle is dependent on resdel, which sets the resonant delay. the voltage applied to resdel determines how far in advance the toggle occurs prior to a lower switch turning on. the zvs transition occurs after the upper switches toggle and before the diagonal lower switch turns on. the required resonant delay is 1/4 of the period of the lc resonant frequency of the circuit formed by the leakage inductance and the parasitic capacitance. the resonant transition may be estimated from equation 25. where is the resonant transition time, l l is the leakage inductance, c p is the parasitic capacitance, and r is the equivalent resistance in series with l l and c p . the resonant delay is always less than or equal to the deadtime and may be calculated using equation 26. where resdel is the desired resonant delay, v resdel is a voltage between 0v and 2v applied to the resdel pin, and dt is the deadtime (see equations 1 through 5). when the upper switches toggle, the primary current that was flowing through ul must find an alternate path. it charges/discharges the parasitic capacitance of switches ul and ll until the body diode of ll is forward-biased. if resdel is set properly, switch ll will be turned on at this time. the output inductor does not assist this transition. it is purely a resonant transition driv en by the leakage inductance. figure 10. ul - lr power transfer cycle vin+ vin- ul ll ur lr vout+ rtn i p i s l l d2 d1 figure 11. ul - ur free-wheeling period vin+ vin- ul ll ur lr vout+ rtn i p i s l l d2 d1 2 -- - 1 1 l l c p -------------- - r 2 4l l 2 --------- - ? ----------------------------------- = (eq. 25) resdel v resdel 2 -------------------- dt ? = s (eq. 26) figure 12. upper switch toggle and resonant transition vin+ vin- ul ll ur lr vout+ rtn l l d2 d1 i s i p isl6752
14 fn9181.3 october 31, 2008 the second power transfer period commences when switch ll closes. with switches ur and ll on, the primary and secondary currents flow, as indicated in figure 13. the ur - ll power transfer period terminates when switch ll turns off, as determined by the pwm. the current flowing in the primary must find an al ternate path. the current flows into the parasitic switch capacitance, which charges the node to vin and then forwar d biases the body diode of upper switch ul. as before, the output inductor current assists in this transition. the primary leakage inductance, l l , maintains the current, which now circulates around the path of switch ur, the transformer primary, and switch ul. when switch ll opens, the output inductor current free wheels predominantly through diode d1. diode d2 may actually conduct very little or none of the free-wheeling current, depending on circuit parasitics. this condition persists through the remainder of the half-cycle. when the upper switches toggle, the primary current that was flowing through ur must find an alternate path. it charges/discharges the parasiti c capacitance of switches ur and lr until the body diode of lr is forward-biased. if resdel is set properly, switch lr will be turned on at this time. the first power transfer period commences when switch lr closes and the cycle repeats. the zvs transition requires that the leakage inductance has sufficient energy stored to fully charge the parasitic capacitances. since the energy stored is proportional to the sq uare of the current (1/2 l l i p 2 ), the zvs resonant transition is load dependent. if the leakage inductance is not able to store sufficient energy for zvs, a discrete inductor may be added in series with the transformer primary. synchronous rectifier outputs and control the isl6752 provides double-ended pwm outputs, outll and outlr, and synchronous rectifier (sr) outputs, outlln and outlrn. the sr outputs are the complements of the pwm outputs. it should be noted that the complemented outputs are us ed in conjunction with the opposite pwm output, i.e. outll and outlrn are paired together and outlr and outlln are paired together. referring to figure 16, the srs alternate between being both on during the free-wheeling portion of the cycle (outll/lr off), and one or the other being off when outll or outlr is on. if outll is on, its corresponding sr must also be on, indicating that outlrn is the correct sr control signal. likewise, if outlr is on, its corresponding sr must also be on, indicating that outlln is the correct sr control signal. a useful feature of the isl6752 is the ability to vary the phase relationship between the pwm outputs (outll, out lr) and their complements (outlln, outlrn) by 300ns. this feature allows the designer to compensate for differences in the propagation times between the pwm fets and the sr fets. a voltage applied to vadj controls the phase relationship. figure 13. ur - ll power transfer cycle vin+ vin- ul ll ur lr vout+ rtn l l d2 d1 figure 14. ur - ul free-wheeling period vin+ vin- ul ll ur lr vout+ rtn i p i s l l d2 d1 figure 15. upper switch toggle and resonant transition vin+ vin- ul ll ur lr vout+ rtn i p i s l l d2 d1 figure 16. basic waveform timing ct outll outlr outlln (sr1) outlrn (sr2) isl6752
15 fn9181.3 october 31, 2008 setting vadj to vref/2 results in no delay on any output. the no delay voltage has a 75mv tolerance window. control voltages below the vref/2 zero delay threshold cause the pwm outputs, outll/lr, to be delayed. control voltages greater than the vref/2 zero delay threshold cause the sr outputs, outlln /lrn, to be delayed. it should be noted that when the pwm outputs, outll/lr, are delayed, the cs to output propagation delay is increased by the amount of the added delay. the delay feature is provided to compensate for mismatched propagation delays between the pwm and sr outputs as may be experienced when one set of signals crosses the primary-secondary isolation boundary. if required, individual output pulses may be stretched or compressed as required using external resistors, capacitors, and diodes. when the pwm outputs are delayed, the 50% upper outputs are equally delayed, so the resonant delay setting is unaffected. on/off control the isl6753 does not have a separate enable/disable control pin. the pwm outputs, outll/outlr, may be disabled by pulling verr to ground. doing so reduces the duty cycle to zero, but the upper 50% duty cycle outputs, outul/outur, will continue operation. likewise, the sr outputs outlln/outlrn will be active high. if the application requires that all outputs be off, then the supply voltage, vdd, must be removed from the ic. this may be accomplished as shown in figure 19. fault conditions a fault condition occurs if vref or vdd fall below their undervoltage lockout (uvlo) thresholds or if the thermal protection is triggered. when a fault is detected the outputs are disabled low. when the faul t condition clears the outputs are re-enabled. an overcurrent condition is not considered a fault and does not result in a shutdown. thermal protection internal die over-temperature protection is provided. an integrated temperature sensor protects the device should the junction temperature exceed +140c. there is approximately +15 c of hysteresis. ground plane requirements careful layout is essential for satisfactory operation of the device. a good ground plane must be employed. vdd and vref should be bypassed directly to gnd with good high frequency capacitance. references [1] ridley, r., ?a new continuous-time model for current mode control?, ieee tr ansactions on power electronics, vol. 6, no. 2, april 1991. figure 17. waveform timing with pwm outputs delayed, 0v < vadj < 2.425v ct outll outlr outlln (sr1) outlrn (sr2) figure 18. waveform timing with sr outputs delayed, 2.575v < vadj < 5.00v ct outll outlr outlln (sr1) outlrn (sr2) figure 19. on/off control using vdd verr outll rtd outlrn outlln vref outur ctbuf ct outul resdel outlr vadj vdd cs gnd +vdd on/off (open = off gnd = on) isl6752 isl6752
16 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9181.3 october 31, 2008 isl6752 shrink small outline plastic packages (ssop) quarter size outline plastic packages (qsop) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of ?b? dimension at maximum material condition. 10. controlling dimension: inches. converted millimeter dimen- sions are not necessarily exact. index area e d n 123 -b- 0.17(0.007) c a m b s e -a- b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 m16.15a 16 lead shrink small outline plastic package (0.150? wide body) symbol inches millimeters notes min max min max a 0.061 0.068 1.55 1.73 - a1 0.004 0.0098 0.102 0.249 - a2 0.055 0.061 1.40 1.55 - b 0.008 0.012 0.20 0.31 9 c 0.0075 0.0098 0.191 0.249 - d 0.189 0.196 4.80 4.98 3 e 0.150 0.157 3.81 3.99 4 e 0.025 bsc 0.635 bsc - h 0.230 0.244 5.84 6.20 - h 0.010 0.016 0.25 0.41 5 l 0.016 0.035 0.41 0.89 6 n16 167 0 8 0 8 - rev. 2 6/04

▲Up To Search▲

Price & Availability of ISL6752AAZA

	To Download ISL6752AAZA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .